Physical Design Engineer II

The Physical Design Engineer II will be responsible for various aspects of silicon engineering, focusing on synthesis, floorplanning, power/grid (P/G) grid design, and timing signoff. This role involves collaborating with ASIC design teams to assess feasibility and tradeoffs in physical design methodologies.

Key Responsibilities

• Perform synthesis, floorplanning, P/G grid design, and timing signoff.
• Develop and improve physical design methods and automation scripts.
• Collaborate with ASIC design teams to study feasibility and tradeoffs.
• Resolve timing and congestion issues and drive execution.
• Run and fix Static Timing Analysis (STA), noise, and physical verification signoff.

Required Skills & Qualifications

• Experience with industry-standard EDA tools.
• Proficiency in scripting languages, particularly Python and TCL.
• Knowledge of deep sub-micron FinFET/CMOS physics.
• Understanding of CMOS digital design principles and standard cells.
• Familiarity with CMOS power dissipation in deep submicron processes.
• Basic knowledge of CMOS analog circuit and physical design.
• Understanding of DFT/Scan/MBIST/LBIST and their impact on physical design flows.