Design Verification Engineer

New

Skills

Design Verification ModelSim Perl scripting Python scripting Questa Real Number Models SystemVerilog HDL UVM methodology VCS simulator Xcelium simulator

We are seeking a Design Verification Engineer to join our innovative team. In this role, you will collaborate with digital, photonics, and analog designers to develop comprehensive test plans and UVM test benches for subsystem verification. You will also contribute to the Golden Reference Model (GRM) and run emulations and formal design verification.

Key Responsibilities
  • Create test plans in collaboration with design teams.
  • Develop UVM test benches for subsystem verification.
  • Support full-chip design verification.
  • Develop Real Number Models for photonics and AMS verification.
  • Contribute to the Golden Reference Model and run emulations.
Required Skills & Qualifications
  • Master's degree in Electrical or Computer Engineering.
  • 1-5 years of industry experience in Design Verification.
  • Proficiency in SystemVerilog HDL.
  • Knowledge of UVM or OVM verification methodologies.
  • Experience with Xcelium, ModelSim, Questa, or VCS simulators.
  • Proficiency in Perl or Python scripting.

No forms. Your profile is generated instantly.

Job Type: Remote

Salary: Not Disclosed

Experience: Entry

Duration: Months

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