Design Verification Engineering

New

Skills

Constrained-Random Verification Coverage Analysis Design Verification Directed Testing Python Scripting Questa SystemVerilog UVM VCS Verdi

We are seeking a Design Verification Subject Matter Expert (DV SME) to oversee deployments and guide verification across various blocks, subsystems, and System-on-Chip (SoC) architectures. This role involves shaping AI-assisted workflows for test generation, regression triage, and coverage closure.

Key Responsibilities
  • Guide verification across blocks, subsystems, and SoC.
  • Shape AI-assisted workflows for test generation and regression triage.
  • Curate evaluations with Forward Deployed Engineers (FDEs) and customer SMEs.
  • Build lightweight prototypes and evaluation harnesses to validate opportunities.
  • Educate and mentor FDEs on verification concepts, tooling, and methodology.
  • Partner with FDEs during customer discovery to translate pain points into actionable plans.
Required Skills & Qualifications
  • Bachelor's or Master's in Electrical Engineering (EE), Computer Engineering (CE), Computer Science (CS), or equivalent.
  • 5+ years of experience in design verification for IP/SoC.
  • Proven success in verifying complex hardware in block, subsystem, and top-level flows.
  • Proficient in SystemVerilog, UVM, and tools like VCS, Questa, and Verdi.
  • Knowledge of constrained-random verification, directed testing, and coverage analysis.
  • Strong understanding of RTL/microarchitecture, memory systems, and interconnects.
  • Experience with Python scripting for building verification tooling or harnesses.

No forms. Your profile is generated instantly.

Job Type: Remote

Salary: Not Disclosed

Experience: Entry

Duration: Months

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