ASIC Design Engineer

New

Skills

ASIC Design FPGA Development RTL Design Scripting (Python) Silicon Validation Standard Bus Protocols SystemVerilog TCL Timing Closure Verilog

Join our team as a New Graduate Engineer specializing in ASIC Design for Starshield projects. This role involves designing cutting-edge digital ASICs and FPGAs, collaborating with various teams to evaluate trade-offs, derive specifications, and ensure successful integration into top-level designs.

Key Responsibilities
  • Design digital ASICs and/or FPGAs for Starshield projects.
  • Evaluate trade-offs and derive specifications in collaboration with modem/DSP and RFIC teams.
  • Define micro-architecture and RTL in Verilog/SystemVerilog.
  • Integrate designs and deliver fully verified, synthesis/timing clean solutions.
  • Work closely with the verification team to cover all design aspects.
  • Provide timing constraints and support the physical implementation team.
  • Participate in silicon bring-up and validation processes.
  • Assist in developing automated test lab equipment for lab measurements.
Required Skills & Qualifications
  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • Graduating in 2026 or 2027 with a relevant degree.
  • 1+ years of RTL implementation and/or FPGA/ASIC development experience.
  • Proficiency in Verilog/SystemVerilog RTL design.
  • Experience with standard bus protocols (AXI, AHB, etc.) and embedded processors.
  • Scripting skills in Python and TCL.
  • Familiarity with simulators like VCS/Questa/IES.

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Job Type: Remote

Salary: Not Disclosed

Experience: Entry

Duration: Months

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