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Sr. RTL Design Engineer

New

Skills

AHB Protocol ASIC Design AXI Protocol Embedded CPU Subsystems Low Power Design Techniques RTL Implementation SoC Integration SystemVerilog Timing Closure Verilog

Join our dynamic team as a Sr. RTL Design Engineer, where you will play a pivotal role in evaluating architectural trade-offs and defining micro-architecture for cutting-edge silicon designs. You will implement RTL in Verilog/SystemVerilog, ensuring that our designs are integrated and verified to meet rigorous standards.

Key Responsibilities
  • Evaluate architectural trade-offs based on features and system limits.
  • Define micro-architecture and implement RTL in Verilog/SystemVerilog.
  • Collaborate with verification teams to ensure complete design verification.
  • Provide timing constraints for IPs and support synthesis and timing closure.
  • Participate in silicon bring-up and validation.
Required Skills & Qualifications
  • Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of RTL implementation experience.
  • ASIC/SoC system integration experience.
  • Experience with embedded CPU subsystems.
  • Familiarity with standard bus protocols such as AXI, AHB, etc.
  • Experience with high-speed and low-power design techniques.

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Job Type: Remote

Salary: Not Disclosed

Experience: Entry

Duration: Months

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