Sr. RTL Design Engineer

New

Skills

ASIC Design Formal Checks Micro-architecture Power Optimization Python Scripting RTL Design SoC Integration SystemVerilog Timing Closure Verilog

Join our team as a Senior RTL Design Engineer where you will play a critical role in evaluating architectural trade-offs and defining micro-architecture in Verilog/SystemVerilog. You will collaborate closely with the verification team to ensure comprehensive coverage and verification of all aspects. This position involves providing timing constraints for IPs and supporting synthesis, timing closure, and formal checks, as well as participating in silicon bring-up and validation.

Key Responsibilities
  • Evaluate architectural trade-offs based on features, performance, and limits.
  • Define micro-architecture and RTL in Verilog/SystemVerilog; integrate and verify.
  • Work with verification team to ensure all aspects are covered and verified.
  • Provide timing constraints for IPs and support synthesis, timing closure, and formal checks.
  • Participate in silicon bring-up and validation.
Required Skills & Qualifications
  • Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of RTL implementation experience.
  • Experience with clock domain crossings and power optimization.
  • ASIC/SoC system integration experience.
  • Proficiency in Python scripting.
  • Ability to work extended hours or weekends as needed for mission-critical deadlines.

No forms. Your profile is generated instantly.

Job Type: Remote

Salary: Not Disclosed

Experience: Entry

Duration: Months

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