Optimizing Processor Cores with Synopsys HPC Design Kit

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Optimizing Processor Cores with Synopsys HPC Design Kit

Introduction to Synopsys High Performance Core (HPC) Design Kit

The Synopsys HPC Design Kit, part of the Foundation IP portfolio, offers a comprehensive suite of high-speed and high-density memories and logic libraries for system-on-chip (SoC) designers. This kit enables designers to optimize processor cores for maximum speed, smallest area, lowest power consumption, or a balanced combination of these factors tailored to their specific application. With optimized standard cells and SRAMs, the HPC Design Kit streamlines the design process by allowing designers to optimize all processors on an SoC using a single package. This integration reduces design costs and accelerates time-to-market for SoC products.

Enhancing Design Capabilities

The latest iteration of the HPC Design Kit enhances the capabilities of SoC designers by offering optimization options for the Synopsys EV6x Embedded Vision Processor's vector DSPs and convolutional neural network (CNN) engines. Designers utilizing the HPC Design Kit for EV6x can achieve significant efficiency improvements in their SoCs, including a 39% power reduction, a 10% decrease in area, or a 7% performance enhancement based on the specific requirements of their target applications. This level of optimization empowers designers to create cutting-edge SoCs that excel in performance, power efficiency, and area utilization.

Comprehensive Component Summary

The HPC Design Kit complements the Duet Package of Embedded Memories and Logic Libraries, providing designers with access to a wide range of memory instances and standard cell libraries optimized for various foundries and process technologies, including GLOBALFOUNDRIES, SMIC, TSMC, and UMC. This comprehensive component summary ensures that designers can leverage the HPC Design Kit across different manufacturing processes and foundries, enhancing the versatility and applicability of the solution.

Enabling Fast and Efficient Design Implementation

In addition to the rich set of memory instances and standard cell libraries, the HPC Design Kit also offers optimized reference scripts and expert core implementation services. These resources are designed to assist design teams in achieving their processor and SoC design objectives efficiently and swiftly. With the support of Synopsys' FastOpt services, designers can implement their optimized processor cores in as little as four to six weeks, significantly reducing design cycle times and expediting time-to-market for their SoC products.

Empowering Core Optimization

The DesignWare HPC Design Kit from Synopsys empowers designers to optimize all on-chip CPU, GPU, and DSP IP cores with a single package that includes high-speed memory instances and standard cell libraries. The kit delivers remarkable results, including up to 39% power reduction, a 10% decrease in area, or a 7% performance improvement for SoCs utilizing the Synopsys ARC EV6x processor. Furthermore, the kit has been validated through collaborations with leading processor IP providers and customers, ensuring its efficacy and reliability in optimizing processor cores for diverse applications.

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