Sr. ASIC Design Engineer (Starshield)

Design digital ASICs/FPGA for Starshield projects.Evaluate trade-offs; derive subsystems specs; partition hardware/software.Define micro-architecture; implement RTL in Verilog/SystemVerilog; deliver verified design.Work with verification team to ensure design is verified.Provide timing constraints for IPs; support synthesis and timing closure.Silicon bring-up and validation; assist in automated test lab equipment.Bachelor’s degree in electrical/computer engineering or CS.5+ years RTL/FPGA/ASIC development.Clock-domain crossings and power optimization.Experience with ASICs and multicore CPU subsystems.Experience with AXI/AHB and embedded processors.EDA tools: VCS/Questa/IES; Spyglass; Vivado/Quartus II.Stock options and long-term incentives.Medical, vision, and dental coverage.401(k) retirement plan.Disability and life insurance.Paid parental leave.3 weeks paid vacation and 10+ holidays.